The present invention relates to a method of fabrication of semiconductor integrated circuit devices and to a semiconductor integrated circuit device, particularly to a fabrication method and a semiconductor integrated circuit device having an alloy of silicon (Si) and germanium (Ge) (hereinafter, simply referred to as SiGe) of polycrystal or single crystal.
With regard to a semiconductor integrated circuit device using SiGe for a gate electrode material, there are descriptions in, for example, J. Vac. Sci. Technol July/August 1997 pl874 through pi880, J. Vac. Sci. Technol July/August 1998 pl833 through pl840 and Japanese Patent Laid-open No. 330463/1999, disclosing a technique for patterning an SiGe gate electrode.
A description will be given of a result of an investigation by the present inventors of a technology for forming a gate electrode having an SiGe layer.
A process of forming a gate electrode having an SiGe layer includes three processing steps, including depositing a gate electrode forming film, patterning the film and postprocessing the patterned film. That is, first, after forming a gate insulating film over a main surface of a semiconductor substrate, a gate electrode forming film having an SiGe layer is deposited thereabove. Successively, after forming a photoresist pattern over the gate electrode forming film, a gate electrode having the SiGe layer is formed by patterning the gate electrode forming film with an etching gas including, for example, chlorine (Cl2) and bromine (Br), using the photoresist pattern as an etching mask. Thereafter, in order to remove Cl, Br and reaction products thereof and reaction products including Si which have adhered to a surface of the semiconductor substrate in forming the gate electrode (hereinafter also referred to as adhered matter), a plasma processing is carried out on the semiconductor substrate in an atmosphere of a predetermined gas (postprocessing).
The postprocessing is a processing which is also carried out after forming the gate electrode by patterning polycrystal silicon; and, when the postprocessing is not carried out, there is a rawback, for example, as follows. That is, when the reaction products are not removed, due to the presence of this foreign matter, the reliability or yield of the semiconductor integrated circuit device is deteriorated. When adhered matter is present on a main face of another semiconductor substrate before patterning the gate electrode, in patterning the gate electrode of the other semiconductor substrate, the adhered matter operates as a mask, and there is produced an etching residue of a gate electrode material. Further, when Cr or Br adhered to the surface of the semiconductor, substrate is not removed, parts of the semiconductor fabricating apparatus are corroded by Cl or Br. Further, Cl or Br is toxic, and, therefore, adverse influence is effected on the human body.
With regard to the gas used in the postprocessing, when SiGe is used as the gate electrode material, there is used, for example, O2/CHF3 since a stable electricity discharge range is provided thereby. Further, this gas is generally used in the postprocessing when polycrystal silicon, is used as the gate electrode material, since an amount of data is enormous and introduction thereof is facilitated. This is similar to the postprocessing when the polycrystal silicon is used as a gate electrode material.
However, according to the technology of forming the gate electrode having an SiGe layer, it has been found for the first time by experiment and evaluation of the inventors that the following problem exists. That is, there is a problem in that so-to-speak side etching is caused in which two side faces of the SiGe layer portion in the gate electrode are polished toward the center.
First, when the inventors evaluated the performance of etching SiGe, it was found that the side etching is liable to occur. Hence, when evaluation had been carried out further in detail, it was found that, although the side etching is not caused in the processing in the etching chamber, the side etching is caused when the postprocessing is carried out in a post processing chamber. Further, it was found that the presence or absence of occurrence of the side etching is dependent upon the concentration of Ge. Further, the shape of the side etching was not improved even after investigating a reduction in the concentration of CHF3, or a reduction in electricity discharge power during postprocessing.
It is an object of the invention to provide a technology capable of improving the shape of a gate electrode having SiGe.
It is other object of the invention to provide a technology capable of promoting the accuracy of dimensions of fabricating a gate electrode having SiGe.
Further, it is another object of the invention to provide a technology capable of promoting the yield of a semiconductor integrated circuit device having a gate electrode having SiGe.
Further, it is a further object of the invention to provide a technology capable of promoting the function of a semiconductor integrated circuit having a gate electrode having SiGe.
Further, it is still another object of the invention to provide a technology capable of simplifying the fabrication steps in the manufacture of a semiconductor integrated circuit device having a gate electrode having SiGe.
Further, it is a still further other object of the invention to provide a technology capable of shortening the development and fabrication time period of a semiconductor integrated circuit device having a gate electrode having SiGe.
The above-described and other objects and novel characteristics of the invention will become apparent from description provided in this specification and the attached drawings.
A simple explanation will be given of an outline of representative aspects of the invention disclosed in the application as follows.
That is, according to an aspect of the invention, there are provided steps of forming a gate electrode having an SiGe layer over a semiconductor substrate by patterning a gate electrode forming film having the SiGe layer and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si.
Further, according to another aspect of the invention, there are provided steps of forming a gate electrode over a semiconductor substrate by patterning a gate electrode forming film deposited on the semiconductor substrate and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive, to Ge and a second gas having a function of etching Si; wherein, and the step of depositing the gate electrode forming film includes a step of depositing an SiGe layer and a step of depositing a polycrystal silicon layer at a layer above the SiGe layer.
Further, according to another aspect of the invention, there are further provided, after the plasma processing, a step of forming side wall insulating films at side faces of the gate electrode, a step of exposing an upper face of the gate electrode and portions of a main face of the semiconductor substrate, a step of depositing a metal film having a high melting point over the semiconductor substrate and a step of forming a metal silicide layer having a high melting point at the upper face of the gate electrode and the portions of the main face of the semiconductor substrate.
Further, according to another aspect of the invention, the metal silicide layer having a high melting point is made of cobalt silicide.
Further, according to another aspect of the invention, there are provided steps of forming a gate electrode over a semiconductor substrate by patterning a gate electrode forming film deposited over the semiconductor substrate and thereafter subjecting the semiconductor substrate to a plasma processing in an atmosphere of a mixed gas of a first gas hardly reactive to Ge and a second gas having a function of etching Si; wherein, the step of depositing the gate electrode forming film includes a step of depositing an SiGe layer and a step of depositing a metal layer at a layer above the SiGe layer.
Further, according to another aspect of the invention, there is provided a step of introducing boron to the SiGe layer.
Further, according to another aspect of the invention, the first gas is constituted by an inert gas.
Further, according to another aspect of the invention, the first gas is constituted by Ar, He, Kr or Xe.
Further, according to another aspect of the invention, the first gas is constituted by nitrogen gas.
Further, according to another aspect of the invention, the second gas is constituted by a gas including fluorine.
Further, according to another aspect of the invention, the second gas is constituted by CHF3, CF4, C2F6 or SF6.
Further, according to another aspect of the invention, when the first gas is constituted by Ar gas, and pressure in the atmosphere is made equal to or smaller than 70 Pa.
Further, according to another aspect of the invention, when the first gas is constituted by Ar gas, the microwave power for forming a plasma is 750 W.
Further, according to another aspect of the invention, when the first gas is constituted by Ar gas and the second gas is constituted by CHF3, the concentration of the second gas is made equal to or smaller than 5% of the total.
Further, according to another aspect of the invention, when the gate electrode forming film having the SiGe layer is patterned, there is carried out a plasma etching processing in an atmosphere of chlorine, bromine or a mixed gas thereof.
Further, according to another aspect of the invention, the concentration of Ge of the SiGe layer is equal to or larger than 10% of the total.
Further, according to another aspect of the invention, the concentration of Ge of the SiGe layer is equal to or larger than 20% of the total.
Further, according to another aspect of the invention, the concentration of Ge of the SiGe layer is equal to or larger than 40% of the total.
Further, according to another aspect of the invention, there is further provided a step of fabricating a semiconductor integrated circuit device in which the semiconductor substrate, after the step of patterning the gate electrode, is transferred to the plasma processing step while maintaining a vacuum state.
Further, according to another aspect of the invention, the side etching amount at two side faces of the gate electrode after the plasma processing is equal to or smaller than 40% of the length in a channel length direction of the gate electrode at a portion thereof other than the SiGe layer.
Further, according to another aspect of the invention, the length in the channel direction of the gate electrode at the SiGe layer, after the plasma processing, is equal to the length in the channel length direction of the gate electrode at the portion other than the SiGe layer.
Further, according to another aspect of the invention, there is a gate electrode of an n-channel type field effect transistor or a p-channel type field effect transistor formed on the same semiconductor substrate for the gate electrode.